1. Field of the Invention
The present invention relates to a semiconductor device with a crystalline semiconductor layer formed on an insulating surface, and particularly to a semiconductor device in which an insulating gate field effect transistor is constructed with a crystalline semiconductor layer being crystallized by laser light irradiation.
2. Description of the Related Art
Technologies of manufacturing an insulating gate field effect transistor by forming an amorphous silicon film on a substrate with an insulating surface and crystallizing the film by laser light irradiation are applied to active matrix liquid crystal display devices, typically flat surface type display devices (flat panel displays).
An example of crystallizing an amorphous semiconductor layer by laser light irradiation is polycrystallization technology, in which a thin film transistor (TFT) is manufactured by irradiating the second harmonic of laser light, emitted using a solid state laser apparatus such as an Nd:YBO4 laser, to an amorphous semiconductor layer, thus forming a crystalline semiconductor layer having a large grain size compared to conventional crystalline semiconductor films, as disclosed in JP 2001-144027 A.
Further, as related technology, in “N. Sasaki et al, 2002 SID International Symposium Digest of Technical Papers, pp. 154-157”, lateral crystal growth by continuous wave laser is reported, and a shift resistor operating at 270 MHz by a TFT manufactured with the technology is disclosed therein.
According to the above document, laser annealing that uses a continuous wave laser oscillator is characterized in that a semiconductor layer is heated by laser light for a longer period of time than when the light source is a pulse laser oscillator, a typical example of which is an excimer laser. The method is also characterized in that crystals grow in a direction that makes the interface between a melt region and a solid phase region roughly parallel to the substrate surface.
It is a known fact that the crystal grain size is varied depending on the thickness of a semiconductor layer that is crystallized by laser annealing. The field effect mobility, which is one of characteristics of a TFT, can be raised by increasing the crystal grain size. FIG. 2 is a graph showing changes in field effect mobility in relation to the thickness of the semiconductor layer and shows a characteristic of an n-channel TFT. The graph compares the characteristic of the TFT of when it receives channel doping (doping with an impurity of one conductivity type the main purpose of which is to control the threshold voltage) (indicated by an outlined triangle) to the characteristic of when there is no channel doping (indicated by an outlined square). According to the graph, higher field effect mobility is obtained in a film thickness range between 70 nm and 150 nm when the TFT does not receive channel doping. On the other hand, the characteristic of when there is channel doping is low in film thickness dependency. The difference is due to the crystallinity being lowered by ions which are implanted into crystals through channel doping.
However, when the TFT does not receive channel doping, the off leak current tends to increase as the thickness of the semiconductor layer is increased, resulting in insufficient ON/OFF ratio. This means that channel doping has an effect of lowering off leak current in addition to the effect of controlling the threshold voltage. In other words, when channel doping is omitted, a rise in gate voltage does not bring enough widening of a depletion layer to leave a not-depleted region deep in the bottom of the semiconductor layer and the not-depleted region forms a so-called back channel which depends solely on the source-drain voltage to cause a current flow. The back channel is formed because of the fact that any amorphous semiconductor layer formed by deposition on a substrate that has an insulating surface exhibits the n type conductivity to a varying degree when crystallized.
This phenomenon has been examined through a simulation performed on the relation between the semiconductor layer thickness and the electric charge density, and the results of the simulation are shown in FIGS. 3 to 6. Calculation in the simulation is made setting the semiconductor layer thickness to 60 mm (FIG. 3), 80 mm (FIG. 4), 100 mm (FIG. 5), and 150 mm (FIG. 6). The subject elements are n-channel TFTs having a single gate structure.
Application of −10 V to the gate and +1 V to the drain is set as a calculation parameter. In this case, electrons which are major carriers in a semiconductor layer that exhibits weak n type conductivity are repelled and move away from the interface of the gate insulating film. Donor ions having positive electric charges remain in the depletion layer. Holes are accumulated at the interface of the gate insulating film to form an inversion layer. When the semiconductor layer has a thickness of 60 nm, most of the semiconductor layer is depleted as shown in FIG. 3. As the thickness of the semiconductor layer exceeds 60 nm, a deeper region away from the interface of the gate insulating film is no longer influenced by the gate voltage and a region where negative electric charges are accumulated is created. Comparison among FIGS. 4 to 6 shows that the accumulation region becomes thicker as the semiconductor layer increases its thickness from 80 nm to 150 nm.
The back channel causes a drain current to flow when the TFT is turned off (off leak current) since a region having the same conductivity type as the source and drain regions is formed to serve as a path through which a drain current flows independent of the gate voltage.
The depletion layer could be widened by electric neutralization through doping with an acceptor impurity which has the opposite conductivity type. However, this measure becomes difficult as the thickness of the semiconductor layer is increased. In particular, in a region located deep in the semiconductor layer, acceptor ions have to be implanted at high acceleration voltage, causing damage in crystals and lowering of the crystallinity. Furthermore, if the acceptor ions accidentally pierce the semiconductor layer and reach the underlying insulating layer, the acceptor ions act as fixed electric charges and cause a change in TFT threshold voltage. This traps carriers and brings a change in characteristic as well as various other inconveniences. In addition, ion implantation or ion shower doping in which ionized impurities are implanted while being accelerated by electric field, is incapable of uniformly distributing ions along the entire depth of the semiconductor layer.